1. Field of the Invention
The present invention relates to display devices to be tested and their associated technologies.
2. Description of the Related Art
Conventionally known as a standard related to a technology for performing high-speed transmission of digital video data is a standard “Digital Visual Interface Revision 1.0” (hereinafter referred to as the DVI standard (see http://www.ddwg.org/)), published on Apr. 2, 1999.
FIG. 23 is a block diagram illustrating a typical digital video data transmit/receive system that is configured according to the DVI standard.
As shown in FIG. 23, this digital video data transmit/receive system comprises a video data transmitter 500, a cable 501, and a display device 502.
The video data transmitter 500 is connected to the display device 502 through the cable 501.
The video data transmitter 500 includes a video generation circuit 503, a data transmission circuit 504, a clock signal generation circuit 505, a control signal transmission circuit 506, and a control signal reception circuit 507.
The display device 502 includes a reception LSI (reception integrated circuit) 508 and a display unit 509. The reception LSI 508 includes a data reception circuit 510, a PLL circuit (Phase Locked Loop) 511, a control signal reception circuit 512, and a control signal transmission circuit 513.
Now, the operation of the system is briefly described below.
As shown in FIG. 23, the control signal transmission circuit 506 of the video data transmitter 500 sends a control signal informing of transmission of video data to the control signal reception circuit 512 of the display device 502 via the cable 501.
The control signal reception circuit 512 then receives the control signal.
The control signal transmission circuit 513 of the display device 502 transmits display control information such as resolutions of the display device 502 to the control signal reception circuit 507 of the video data transmitter 500 via the cable 501.
The clock signal generation circuit 505 of the video data transmitter 500 generates a clock signal and sends it to the video generation circuit 503 and the PLL circuit 511 of the display device 502.
The video generation circuit 503 outputs video data in sync with the clock signal supplied by the clock signal generation circuit 505.
Then, the data transmission circuit 504 transmits the video data outputted by the video generation circuit 503 to the data reception circuit 510 of the display device 502 via the cable 501.
The data reception circuit 510 of the display device 502 captures the video data in sync with a timing signal that is generated by the PLL circuit 511 in sync with the clock signal.
The data reception circuit 510 outputs the captured video data to the display unit 509, on which the video data is in turn displayed.
Conventionally, image disturbances appearing on the display unit 509 are visually inspected or data error rates are measured to check the operation of such the digital video data transmit/receive system.